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XR18W750
WIRELESS UART CONTROLLER
REV. 1.0.0
IER[5]: Reserved
For normal operation, this bit should be ’0’.
IER[6]: RTS# Output Interrupt Enable (requires EFR bit-4=1)
? Logic 0 = Disable the RTS# interrupt (default).
? Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition
from low to high.
IER[7]: CTS# Input Interrupt Enable (requires EFR bit-4=1)
? Logic 0 = Disable the CTS# interrupt (default).
? Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from
low to high.
5.4
Interrupt Status Register (ISR) - Read-Only
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table, Table 9 , shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources
associated with each of these interrupt levels.
5.4.1
Interrupt Generation:
? LSR is by any of the LSR bits 1, 2, 3 and 4.
? RXRDY is by RX trigger level.
? RXRDY Time-out is by a 4-char plus 12 bits delay timer.
? TXRDY is by TX trigger level or TX FIFO empty.
? MSR is by any of the MSR bits 0, 1, 2 and 3.
? CTS# is when its transmitter toggles the input pin (from LOW to HIGH) during auto CTS flow control.
? RTS# is when its receiver toggles the output pin (from LOW to HIGH) during auto RTS flow control.
5.4.2
Interrupt Clearing:
? LSR interrupt is cleared by a read to the LSR register.
? RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
? RXRDY Time-out interrupt is cleared by reading RHR.
? TXRDY interrupt is cleared by a read to the ISR register or writing to THR.
? MSR interrupt is cleared by a read to the MSR register.
? RTS# and CTS# flow control interrupts are cleared by a read to the MSR register.
]
T ABLE 9: I NTERRUPT S OURCE AND P RIORITY L EVEL
P RIORITY
ISR R EGISTER S TATUS B ITS
S OURCE OF INTERRUPT
L EVEL
B IT -5
B IT -4
B IT -3
B IT -2
B IT -1
B IT -0
1
2
3
4
5
7
-
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
1
LSR (Receiver Line Status Register)
RXRDY (Receive Data Time-out)
RXRDY (Received Data Ready)
TXRDY (Transmit Ready)
MSR (Modem Status Register)
CTS#, RTS# change of state
None (default) or Wake-up Indicator
22
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